A CDE Definition
(Intel Architecture-64) The 64-bit architecture used in Intel's Itanium family of CPU chips. Engineered for server processing, Itanium/IA-64 was designed when millions more transistors on a chip were commonplace, which was two decades after Intel developed its first x86 CPUs. Later on, Intel also upgraded the x86 line to 64 bits (see Intel 64). See Itanium and x86.
Although applications written for x86 and HP 9000 computers run intact on IA-64 machines via translation layers (see IA 32 Execution Layer), programs have to be recompiled in order to take advantage of IA-64.
Rather than variable-length instructions as in x86 (IA-32), IA-64 uses fixed-length, four-byte instructions bundled in sets of three "long instruction words." IA-64 uses 256 registers for integer and floating point operations compared to 16 in IA-32.
IA-64 Predicts the Future
To take advantage of an advanced pipeline architecture, IA-64 employs "predication." Both sides of a branch instruction following a compare are executed in parallel. After determining which branch is correct, the results of the other are discarded. IA-64 compilers have to set up the predication; they have to interleave the instructions and add codes that tell the CPU how to execute in parallel. If predication is not set up, the CPU performs a simpler prediction, whereby it executes in parallel the side of the branch that it thinks will be the outcome, not both sides. If it guesses wrong, the parallelism is lost for those few nanoseconds.
IA-64 also supports speculative loading, which loads data into registers before the instructions actually need to process it. Intel brands this parallel architecture "Explicitly Parallel Instruction Computing" (EPIC), and sometimes refers to the IA-64 architecture as EPIC; thus, IA-64 and EPIC are synonymous.
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