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The code name for a family of multicore GPGPU chips from Intel that was announced in 2007 and dropped in 2010. Based on the x86 architecture, Larrabee chips were expected to have up to 16 cores, share a large L2 cache and include a memory controller. They were designed to provide a very flexible computing environment, not only for graphics rendering, but also for encryption and other parallel processing applications. See GPGPU and Tera-Scale.

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